SOI Substrates Glossary

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A

Anneal

Process to alter wafer properties by heating. An example is a bond anneal where wafers are heated in a furnace to form strong bonds between the handle and device wafers in the formation of SOI.

Applications

SOI is used in a wide range of areas such as MEMS/MST, BioMEMS, RF MEMS, Optoelectronics, Smart Power, Integrated sensors, advanced analog ICs.

B

BCO Substrate™

Now known as SOI + Trench & Refill. Customised trench-isolated SOI substrate for low to high voltage applications, containing fully dielectrically isolated Si tubs, with optional sidewall doping and buried doped layer. Provides die shrinkage and electrical performance advantages over conventional technologies.

BCO Technologies

Company formed in Belfast in 1992 and later acquired by Analog Devices Inc. Icemos Technology occupies the former BCO site

BESOI

Bond and Etch back SOI.

Bonded SOI

SOI formed by bonding a device quality silicon wafer to a handle silicon wafer. Either or both of the two silicon wafers may have an oxide layer to form the BOX.

Buried oxide, BOX

Buried oxide layer- the insulating layer between the handle and device wafers.

C

Chemical Mechanical Polish, CMP

A process for the removal of surface material from a wafer using chemical and mechanical actions to achieve a flat surface prior to subsequent processing.

Complementary metal-oxide semiconductor, CMOS

In CMOS technology, both N-type and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs).

Crosstalk

Crosstalk and interference between devices in mixed signal ICs is reduced when SOI is used due to the isolation of devices from the substrate.

Customised SOI

SOI products offered by Icemos Technology, Belfast offering many different user-defined variations. See Products and Services.

D

Device Layer

Single crystal silicon layer of SOI on which devices are fabricated.

Dielectric Isolation

Devices are isolated from each other and the substrate by forming tubs separated by a dielectric material.

Doping, n-type, p-type

Impurity doping is the introduction of controlled amounts of impurity dopants into semiconductors either by diffusion or ion implantation. For silicon, boron and phosphorus are the most common dopants for p- and n-type materials, respectively.

DRIE

Deep reactive ion etching is used to etch deep cavities in substrates with relatively high aspect ratio.

E

Etch

Process by which material is removed from the wafer in a pattern already transferred lithographically. This may be achieved chemically in a process referred to as wet etching, or in a plasma, where a controlled gas flow is ionised and reacts with surface material on the wafer.

F

Fully depleted SOI, FD SOI

SOI where the device layer is thinner than the depletion width beneath the channel and the depletion region extends to the buried oxide.

G

Growth method, FZ, CZ

Methods of growing single crystal silicon, float-zoning (FZ) and Czochralski growth (CZ).

H

Handle wafer

The base silicon substrate on which the insulating and active device layers are formed.

HVIC

High Voltage Integrated Circuit. HVICs are used for many applications including smart power devices, telecommunications and display.

I

Insulator

An insulator is a material used to separate conducting materials. In the case of SOI, the SiO₂ layer is used as to isolate silicon regions.

L

Latch-up

Latch-up and leakage in CMOS structures are eliminated for SOI designs due to the isolation of the active device from the substrate.

M

MEMS, MST

Micro-Electro-Mechanical Systems micromachined in silicon and integrated with electronics. SOI is ideal for fabricating e.g. microsensors because the Si/BOX interface provides a perfect etch stop. In this way very thin membranes may be produced. Sectors within include BioMEMS, RF MEMS, Optical MEMS, MOEMS, Inertial MEMS.

Metal-oxide semiconductor, MOS

3-layer MOS structures are used as gates in MOSFETs.

O

Oxidation, oxidization

Process by which SiO₂ is thermally grown on silicon.

P

Parasitic capacitance

The capacitive leakage across a device when formed in bulk silicon. Use of SOI reduces the effect.

Partially depleted SOI, PD SOI

SOI in which the device layer is thick enough for the depletion width not to reach the buried oxide so that a neutral region exists below the channel and depletion region.

Power consumption

Devices can operate at lower power due to the reduction in parasitic capacitance. Alternatively, at the same power, devices can operate at faster speeds.

R

Resistivity

Resistance per unit area, units Ohm-cm.

RIE

Reactive Ion Etch. Plasma process technology for etching pre-patterned structures into substrates.

S

Sectors

Sectors using SOI include telecommunications, automotive, consumer electronics, commerce, aerospace, medical, instrumentation.

Silicide

Alloy of silicon and a metal. Some metal silicides show low Resistivity and high thermal stability. Examples include WSi₂, TiSi₂ and CoSi₂.

Silicon direct bonding

See Silicon fusion bonding.

Silicon fusion bonding

Method of producing SOI or silicon-silicon wafers with an almost limitless combination of BOX and film thicknesses where an oxidised wafer is joined to another wafer.

Silicon oxide, SiO₂

Insulator used in SOI wafers. May be grown thermally or deposited by chemical vapour deposition.

Silicon, Si

Material used for much of the world's semiconductor devices.

Silicon-on-insulator, SOI

Substrate structure offering many advantages over CZ bulk or epi wafers such as low leakage, higher transistor densities, reduced parasitic capacitance, lower power consumption, faster speed and enhanced radiation hardness. SOI dielectrically separates the active device layer from the substrate using a buried oxide.

Silicon-on-Sapphire, SOS

Initial member of the SOI family.

Silicon-silicon, Si-Si

Silicon-silicon wafers are bonded substrates containing several layers of single crystal silicon. This produces a high quality wafer with low leakage, low warpage, and a low defect density with small thickness deviation in the substrate.

SIMOX

Separation by IMplanted OXygen process where a high dose ion implantation of oxygen and high temperature anneal form the BOX layer in a bulk wafer to form a thin-film SOI.

STI

Shallow trench isolation.

T

Thick film SOI

SOI wafers where the device layer is approximately 2µm or greater. See also SOI.

Transistor

Semiconductor device for switching or amplifying signals.

Trench

Structure formed in wafer to enable fabrication of devices. See Etch also.

Trench Isolation

Dielectric isolation of silicon using vertically etched isolation trenches lined with oxide and refilled with polysilicon.

W

Wafer bonding

See Silicon fusion bonding.